FIG. 1 shows an exemplary configuration of a conventional band gap reference voltage generating circuit for outputting a reference voltage free from temperature dependency. This circuit is also termed a “Band-Gap-Referenced Biasing Circuit”. As for this sort of the circuit, reference is to be made to the description of, for example, Non-Patent publication 1. The reference voltage generating circuit includes PNP bipolar junction transistors (herein abbreviated to BJT transistors) Q1 and Q2, a differential amplifier A1 and resistors R1 and R2.
To an emitter of the BJT Q1, which has a base and a collector connected to the ground potential, is connected one end of the resistor R1, the other end of which is connected to an output of the differential amplifier A1. The resistor R2 has its one end connected to an emitter of the BJT Q2, a base and a collector of which are connected to the ground potential. The resistor R2 has its other end connected to the one end of the resistor R1, the other end of which is connected to an output of the differential amplifier A1. A node N1 between the resistor R1 and the emitter of the BJT Q1 and a node N2 between the resistors R1 and R2 are connected to the non-inverting input terminal and to the inverting input terminal of the differential amplifier A1, respectively. Meanwhile, with the N-well process, it is possible to form a structure operating as a PNP bipolar junction transistor, in which a P+ region in the N-well becomes an emitter, the N-well becomes a base and the P-substrate becomes a collector, which is connected to the ground potential (see Non-Patent Document 1).
The emitter size ratio of the BJTs Q1 and Q2 is such that AE (Q1): AE (Q2)=1:N. An output voltage VREF of the circuit, described above, may be determined by the following method.
The nodes N1 and N2 become equal to each other in potential due to negative feedback of the differential amplifier A1. Hence, the currents flowing through the two resistors R1 become equal to each other, while the currents flowing through the BJTs Q1 and Q2 (collector currents) also become equal to each other.
Since the emitter area of the BJT Q2 is larger than that of the BJT Q1, the base-to-emitter voltage VBE2 of the BJT Q2 becomes smaller than the base-to-emitter voltage VBE1 of the BJT Q1, and the differential voltage Δ VBE between the two voltages VBE1, and VBE2 is applied to the resistor R2. This potential difference Δ VBE=VBE1−VBE2 is given by the following equation (1):
                              Δ          ⁢                                          ⁢                      V            BE                          =                                            k              ⁢                                                          ⁢              T                        q                    ⁢          ln          ⁢                                          ⁢          N                                    (        1        )            
The derivation of the equation (1) will now be briefly described. Since the collector currents I1 and I2 of the BJTs Q1 and Q2 are given respectively by I1=Isexp(qVBE1/(kT)) and I2=Isexp(qVBE2/(kT)), where Is denotes the saturation current, k the Boltzmann constant, T the absolute temperature and q denotes the electrical charge of an electron (unit electrical charge), the base-to-emitter voltages of Q1 and Q2 may be expressed as VBE1=(kT/q)1n(I1/Is) and VBE2=(kT/q)1n(I2/Is), respectively. Hence,
                                          Δ            ⁢                                                  ⁢                          V              BE                                =                    ⁢                                                    V                                  BE                  ⁢                                                                          ⁢                  1                                            -                              V                                  BE                  ⁢                                                                          ⁢                  2                                                      =                                                            (                                      k                    ⁢                                                                                  ⁢                                          T                      /                      q                                                        )                                ⁢                                                                  ⁢                                  ln                  ⁡                                      (                                                                  I                        1                                            /                                              I                        s                                                              )                                                              -                                                (                                      k                    ⁢                                                                                  ⁢                                          T                      /                      q                                                        )                                ⁢                                                                  ⁢                                  ln                  ⁡                                      (                                                                                            I                          2                                                /                        N                                            ⁢                                                                                          ⁢                                              I                        s                                                              )                                                                                      )                                =                ⁢                              (                          k              ⁢                                                          ⁢                              T                /                q                                      )                    ⁢                                          ⁢          ln          ⁢                                          ⁢                      (                          N              ⁢                                                          ⁢                                                I                  1                                /                                  I                  2                                                      )                              so that, when I1=I2, the above equation (1) is derived.
The current I2, flowing through the resistor R2, is given by the following equation (2):
                              I          2                =                                            Δ              ⁢                                                          ⁢                              V                BE                                                    R              2                                =                                                                      k                  ⁢                                                                          ⁢                  T                                                                      R                    2                                    ⁢                  q                                            ⁢              ln              ⁢                                                          ⁢              N                        =                          I              1                                                          (        2        )            
Hence, the output voltage VREF of the differential amplifier A1 is given by the following equation (3):
                              V          REF                =                                            V                              BE                ⁢                                                                  ⁢                1                                      +                                          R                1                            ⁢                              I                1                                              =                                    V                              BE                ⁢                                                                  ⁢                1                                      +                                                            R                  1                                                  R                  2                                            ⁢                                                k                  ⁢                                                                          ⁢                  T                                q                            ⁢              ln              ⁢                                                          ⁢              N                                                          (        3        )            
In the above equation (3), VREF of the first term has negative temperature dependency, that is, has a negative temperature coefficient, meaning that the higher the temperature, the lower becomes the voltage.
(R1/R2)(kT/q)1nN of the second term is proportionate to the absolute temperature T, that is, the term has positive temperature dependency.
Thus, by suitably adjusting the ratio between the resistances of the resistors R1 and R2, it is possible to cancel out the temperature dependency of the output voltage VREF.
The voltage VREF obtained in this manner is termed the ‘band-gap voltage’ and amounts to 1.2 to 1.3V with the BJT of Si. The currents I1 and I2 are proportionate to the absolute temperature T and hence are termed the proportionate-to-absolute temperature current, abbreviated to PTAT current.
The circuit of this sort is roughly divided into a PTAT current generating section and a reference voltage generating section. In FIG. 1, the resistors R1 and R2 and the BJTs Q1 and Q2 correspond to the PTAT current generating section, while the resistor R1 and the BJT Q1 correspond to the reference voltage generating section. The BJT Q1 is common to the PTAT current generating section and to the reference voltage generating section.
In general, the base-to-emitter voltage VBE suffers from only little process variations. Hence, if the differential amplifier is an ideal amplifier, it is possible to implement a reference voltage having extremely small variations.
However, MOS transistors arranged proximately are in general subjected to variations in the threshold voltage VT which are as large as several mV to tens of mV. For this reason, with a differential amplifier employing MOS transistors, an offset voltage ascribable to the threshold voltage variations is generated.
This offset voltage summed for the entire circuit and referred as the input voltage of the differential amplifier is the so-called input referred offset voltage. In FIG. 1, VOS denotes the input referred offset voltage.
FIG. 6 is a diagram showing the configuration of a typical example of a differential amplifier formed by MOS transistors. The differential amplifier includes N-channel MOS transistors M1 and M2, which constitute a differential pair, and have sources connected in common, and have gates supplied with voltages VIN− and VIN+, respectively. The differential amplifier also includes P-channel MOS transistors M3 and M4 of the current mirror configuration, which are connected between a power supply VEXT and the drains of N-channel MOS transistors M1 and M2, and which constitute an active load of the differential pair. The differential amplifier also includes an N-channel MOS transistor M5, which is connected between the coupled sources of the N-channel MOS transistors M1 and M2 and the ground and which constitutes a constant current source. The differential amplifier further includes a P-channel transistor M6, which is connected between the power supply VEXT and an output terminal VOUT and which has a gate connected to a connection node of the drains of the transistors M4 and M2, and an N-channel MOS transistor M7 which is connected between the output terminal VOUT and the ground and which constitutes a constant current source. A bias voltage VBIAS is supplied to the gates of the N-channel MOS transistors M5 and M7.
In this differential amplifier, it is the differential transistor pair M1 and M2 of the input stage that affects, above all, the input referred offset.
The relationship between the offset voltage VOS and the output voltage VREF may be represented by the following equation (4):
                                                                                                              ⅆ                                          V                      REF                                                                            ⅆ                                          V                      OS                                                                      ⁢                                  |                                                            V                      OS                                        ->                    0                                                              =                            ⁢                                                                    ⅆ                                          V                                              BE                        ⁢                                                                                                  ⁢                        1                                                                                                  ⅆ                                          V                      OS                                                                      ⁢                                  |                                                            V                      OS                                        ->                    0                                                  ⁢                                                      +                                          R                      1                                                        ⁢                                                            ⅆ                                              I                        1                                                                                    ⅆ                                              V                        OS                                                                                            ⁢                                  |                                                            V                      OS                                        ->                    0                                                                                                                          =                            ⁢                              1                +                                  2                                      ln                    ⁢                                                                                  ⁢                    N                                                  +                                                      R                    1                                                        R                    2                                                  +                                                                            R                      2                                        ⁡                                          (                                              1                        +                                                                              1                            /                            ln                                                    ⁢                                                                                                          ⁢                          N                                                                    )                                                                                                  R                      1                                        ⁢                                                                                  ⁢                    ln                    ⁢                                                                                  ⁢                    N                                                                                                                          >                            ⁢              10                                                          (        4        )            
The above solution (4) may be found by differentiating the following two equations (5) and (6) with regard to VOS. The equation (5) expresses that, in FIG. 1, the voltage across the terminals of the resistor R2 is equal to the sum of the differential voltage Δ VBE of the base-to-emitter voltages of the BJTs Q1 and Q2 and the offset voltage VOS. The equation (6), on the other hand, expresses that the difference between the voltage at the node N1 and that at the node N2 is equal to the offset voltage VOS.
                                          I            2                    ⁢                      R            2                          =                                            V                              BE                ⁢                                                                  ⁢                1                                      -                          V                              BE                ⁢                                                                  ⁢                2                                      +                          V              OS                                =                                                                      k                  ⁢                                                                          ⁢                  T                                q                            ⁢              ln              ⁢                                                          ⁢                                                N                  ⁢                                                                          ⁢                                      I                    1                                                                    I                  2                                                      +                          V              OS                                                          (        5        )                                                                    I              1                        ⁢                          R              1                                -                      V            OS                          =                              I            2                    ⁢                      R            1                                              (        6        )            
It is seen from the above equation (4) that, in the circuit configuration of FIG. 1, the offset voltage VOS is multiplied by 10 or more and the so multiplied voltage is output as an output of the differential amplifier A1.
The voltage of this magnitude is non-negligible even in normal applications. It is therefore necessary to trim the resistor R1 or R2 with a laser trimming equipment or an electrical fuse.
On the other hand, in the circuit configuration of FIG. 1, the output voltage VREF is 1.2V to 1.3V. Thus, the voltage at least 1.3V or higher is needed as the power supply VEXT, as shown in FIG. 7. Meanwhile, FIG. 7 shows the relationship between the output voltage VOUT (VREF) on the vertical axis and the power supply voltage VEXT on the horizontal axis, for the conventional circuit and the present invention as later described.
FIG. 2 shows the circuit configuration disclosed in Patent Document 1 (JP Patent Kokai Publication No. JP-A-8-320730). Referring to FIG. 2, an NPN BJT Q1 has an emitter directly connected to the ground potential, that is, grounded, while an NPN BJT Q2 has an emitter connected via resistor R2 to the ground potential. The collectors of the BJTs Q1 and Q2 are connected to the non-inverting input terminal (+) and to the inverting input terminal (−) of the differential amplifier A1, respectively. One ends of three resistors R0, R0 and R1 are connected in common to an output terminal of the differential amplifier A1, while the other ends of the resistors R0 and R0 are connected to the collectors of the BJTs Q1 and Q2 and the other end of the resistor R1 is connected to the collector and the base of the NPN BJT Q3. A resistor R3 is connected between the base of the BJT Q1 and the base of the BJT Q2. The ratio of the emitter sizes of the BJTs Q1 and Q2 is set to 1:N, where N is a preset positive integer. In this configuration, a resistor R2 for generating Δ VBE is connected to the emitter of the NPN BJT and feedback to the differential amplifier A1 is via collector terminal of the NPN BJT.
In the reference voltage generating circuit of FIG. 2, the PTAT current generating section for generating the PTAT current, is made up of the resistors R0, R2 and R3, and BJTs Q1 and Q2. The reference voltage generating section for generating the voltage having the negative temperature coefficient, is made up of the resistor R1 and the BJT Q3.
As may be seen from equations (8), (9) and (10), which will be explained later, the collector currents I1, I2 and I3 of the BJTs Q1, Q2 and Q3 are of values proportional to one another, and are all PTAT currents. The output voltage VREF of this circuit is the sum of the base-to-emitter voltage VBE3 of the transistor Q3 and the voltage across the terminals of the resistor R1, or R1·I3, and may be represented by the following equation (7):VREF=VBE3+R1I3  (7)
Since the base-to-emitter voltage VBE3 of the transistor Q3 exhibits negative temperature dependency, that is, has a negative temperature coefficient, and the current I3 exhibits positive temperature dependency, that is, has a positive temperature coefficient, a band gap voltage having temperature dependency cancelled out, may be obtained by adjusting appropriately the resistance of the resistor R1, as in the circuit of FIG. 1.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-8-320730
[Non-Patent Document 1]
Behzad Razavi, “Designing of Analog CMOS Integrated Circuit”, pages 470-471, FIG. 11.11, translated by Tadahiro Kuroda, published by Maruzen Co. Ltd.